Xilinx Design Summary

LAB1 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	56	3,840	1%
Number of 4 input LUTs	46	3,840	1%
Logic Distribution
Number of occupied Slices	64	1,920	3%
Number of Slices containing only related logic	64	64	100%
Number of Slices containing unrelated logic	0	64	0%
Total Number of 4 input LUTs	46	3,840	1%
Number of bonded IOBs	15	173	8%
Number of GCLKs	1	8	12%
Number of RPM macros	16
Total equivalent gate count for design	727
Additional JTAG gate count for IOBs	720

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met